PIC18F45K20-I/MV【PDF 221/234 页】MCU 32KB FLASH 1536B RAM 40-UQFN

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3873

217页 218页 219页 220页 [221页]222页 223页 224页 225页

2007 Microchip Technology Inc.

Preliminary

DS70165E-page 85

dsPIC33F

TABLE 5-1:

RESET FLAG BIT OPERATION

5.1

Clock Source Selection at Reset

If clock switching is enabled, the system clock source at

device Reset is chosen, as shown in Table 5-2. If clock

switching is disabled, the system clock source is always

selected according to the oscillator Configuration bits.

Refer to Section 8.0 “Oscillator Configuration” for

further details.

TABLE 5-2:

OSCILLATOR SELECTION vs.

TYPE OF RESET (CLOCK

SWITCHING ENABLED)

5.2

Device Reset Times

The Reset times for various types of device Reset are

summarized in Table 5-3. The system Reset signal,

SYSRST, is released after the POR and PWRT delay

times expire.

The time at which the device actually begins to execute

code also depends on the system oscillator delays,

which include the Oscillator Start-up Timer (OST) and

the PLL lock time. The OST and PLL lock times occur

in parallel with the applicable SYSRST delay times.

The FSCM delay determines the time at which the

FSCM begins to monitor the system clock source after

the SYSRST signal is released.

bit 0

POR: Power-on Reset Flag bit

= A Power-up Reset has occurred

= A Power-up Reset has not occurred

Flag Bit

Setting Event

Clearing Event

TRAPR (RCON<15>)

Trap conflict event

POR

IOPUWR (RCON<14>)

Illegal opcode or uninitialized

W register access

POR

EXTR (RCON<7>)

MCLR Reset

POR

SWR (RCON<6>)

RESET

instruction

POR

WDTO (RCON<4>)

WDT time-out

PWRSAV

instruction, POR

SLEEP (RCON<3>)

PWRSAV #SLEEP

instruction

POR

IDLE (RCON<2>)

PWRSAV #IDLE

instruction

POR

BOR (RCON<1>

BOR

—

POR (RCON<0>)

POR

—

Note:

All Reset flag bits may be set or cleared by the user software.

REGISTER 5-1:

RCON: RESET CONTROL REGISTER(1)

Note 1:

All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

Reset Type

Clock Source Determinant

POR

Oscillator Configuration bits

(FNOSC<2:0>)

BOR

MCLR

COSC Control bits

(OSCCON<14:12>)

WDTR

SWR

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式